Volume-2 Issue-2, September 2022 – Indian Journal of VLSI Design (IJVLSID)

A1212033123

IJVLSID Journal — Wed, 20 Dec 2023 11:19:06 +0000

The Indian Journal of VLSI Design (IJVLSID) has ISSN 2582-8843 (online), open-access, peer-reviewed, periodical half-yearly international journal, which is published by Lattice Science Publication (LSP) in March and September. The journal aims to publish high-quality peer–reviewed original articles in the area of VLSI Design that covers VLSI Circuits and Design, Biological Computing, Computer-Aided Design (CAD), Fault-Tolerance, Emerging Technologies, Low Power and Power Aware Design, Molecular Computing, Nano Electronics Computing, Post-CMOS VLSI, Reliability, Testing, VLSI Applications (Communications, Video, Security, Sensor Networks), Quantum Computing and Wireless Communications. #VLSI Circuits and Design #Biological Computing #Computer-Aided Design (CAD) #Fault-Tolerance #Emerging Technologies #Low Power and Power Aware Design #Molecular Computing #Nano Electronics Computing #Post-CMOS VLSI #Reliability #Testing #VLSI Applications (Communications, Video, Security, Sensor Networks) #Quantum Computing #PhD ademic #Scopus #SCI #LatticeScience #Springer, #ScienceDirect #IEEE #Mendeley #Research #Scholarship #UGC #SSRN #LatticeScience #ESCI #Science #Journal #Conference #SSRN #PubLons

Design of Smart Alu with Error Detection and Correction at Input Side
Abinet Arba

Abinet Arba, (MSc) Lecturer, Department of Electrical and Computer Engineering, Woliata Sodo University Ethiopia.

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© The Authors. Published by Lattice Science Publication (LSP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: We are moving towards the era of scaling down of transistor size, short channel effects (SCEs) and errors are becoming major concern. NSFET is emerging transistors, which gives better SCEs performance compared to conventional MOSFET and FinFET transistors. In this paper, (7, 4) Hamming code was implemented at input side of ALU to prevent error which occur when the transistors size decreases (scale down). The efficiency of any system depends on the performance of internal components. If internal components satisfy the criteria of area, power and delay, the system will always be a efficient system, therefore in this paper the smart ALU was designed by making the internal components to satisfy criteria of area, power and delay. All internal components of ALU including (7, 4) Hamming code was designed by using MICROWIND 3.9 and DSCH 3.9 software and each component design was started from schematic diagram and moved up to automatic physical design by using Verilog code and including post layout simulation with spice netlist which contains parasitic parameters and finally area, power consumption, propagation delay including global delay analysis with RC information and operating frequency of each internal components of ALU was measured and compared with existing one and also Number of error detected and corrected was measured. Two kind of technology was used depending on their advantages (3nm technology for arithmetic design and 7nm technology for remain component design).

Keywords: NSFET, Fin FET, SCEs, Error, (7, 4) Hamming code, MICROWIND 3.9, DSCH 3.9, schematic diagram, physical design, Verilog code.
Scope of the Article: VLSI Circuits and Design

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B1210092222

IJVLSID Journal — Sat, 03 Sep 2022 08:48:36 +0000

Low-Power 6T SRAM Cell using 22nm CMOS Technology
Nibha Kumari¹, Vandana Niranjan²

¹Nibha Kumari, Department of Electronics & Communication Engineering, Indira Gandhi Delhi Technical University, Women Delhi, India.

²Prof. Vandana Niranjan, Department of Electronics & Communication Engineering, Indira Gandhi Delhi Technical University, Women Delhi, India.

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© The Authors. Published by Lattice Science Publication (LSP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Static Random-Access Memory (SRAM) occupies approximately 90% of total area on a chip due to high number of transistors used for a single SRAM cell. Therefore, SRAM cell becomes a power-hungry block on a chip and it becomes more prominent at lower technologies from both dynamic and static perspective. Static power consumption is due to leakage current associated with the transistors that are off and dynamic power consumption is due to charging and discharging of the circuit capacitance. As gate length or channel length decreases gate oxide thickness also scales down. Scaling down of conventional transistor results in huge tunneling of electron from gate into channel leading to higher leakage power consumption. So, transistor with metal gate, high-k dielectric and strained-Si is used which shows better result in terms of low-power consumption, better performance with acceptable delay. Among various topologies of SRAM cell 6T is considered as a suitable choice for low power applications.

Keywords: SRAM, Metal Gate/ High-k/ Strained-Si, Metal Gate/ High-k, Power Consumption
Scope of the Article: VLSI Circuits and Design

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D1209091422

IJVLSID Journal — Sat, 30 Jul 2022 09:16:20 +0000

Low Power ALU using Wave Shaping Diode Adiabatic Logic
Ishita Khindria¹, Kashika Hingorani², Vandana Niranjan³

¹Ishita Khindria, Department of Electronics and Communications, Indira Gandhi Delhi Technical University for Women, Delhi, India.

²Kashika Hingorani, Department of Electronics and Communications, Indira Gandhi Delhi Technical University for Women, Delhi, India.

³Vandana Niranjan, Department of Electronics and Communications, Indira Gandhi Delhi Technical University for Women, Delhi, India.

Manuscript received on 16 July 2022 | Revised Manuscript received on 23 July 2022 | Manuscript Accepted on 15 September 2022 | Manuscript published on 30 September 2022 | PP: 1-4 | Volume-2 Issue-2, September 2022. | Retrieval Number: 100.1/ijvlsid.D1209091422 | DOI: 10.54105/ijvlsid.D1209.091422

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© The Authors. Published by Lattice Science Publication (LSP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: The evolution of portable electronic devices and their widespread application has led to an increased focus on power dissipation as one of the critical parameters. An increase in functionality requirement and design complexity on a single chip has resulted in increased power dissipation. High power dissipation has motivated study and innovation on low power circuit design techniques. Adiabatic logic has been studied as one of the design techniques to reduce power dissipation by reusing the power that was getting dissipated in conventional designs. This paper presents the application of Wave Shaping Diode Adiabatic Logic (WSDAL) to implement an ALU and analyse the improvement in power dissipation as compared to the conventional CMOS design. The WSDAL design uses a slow and time-fluctuating 2-phase sinusoidal Power Clock (PC), which supplies power as well as a clock to the designs. WSDAL uses an Ultra-Low Power Diode (ULPD) structure that operates as a wave shaping device and reduces glitches at the output. The design has been implemented in OrCAD Capture and simulated using Pspice in TSMC 180nm technology. The simulations were performed at 200MHz PC frequency and power dissipation was studied over a range of voltages from 1.4V to 2.2V. The simulations show that WSDAL ALU dissipates less power than the CMOS design. This study indicates that WSDAL-based designs have the potential to be deployed for power dissipation reduction in portable devices.

Keywords: Adiabatic, ALU, Low Power Design, WSDAL.
Scope of the Article: VLSI Circuits and Design

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