Low-Power 6T SRAM Cell using 22nm CMOS Technology
Nibha Kumari1, Vandana Niranjan2
1Nibha Kumari, Department of Electronics & Communication Engineering, Indira Gandhi Delhi Technical University, Women Delhi, India.
2Prof. Vandana Niranjan, Department of Electronics & Communication Engineering, Indira Gandhi Delhi Technical University, Women Delhi, India.
Manuscript received on 14 August 2022 | Revised Manuscript received on 27 August 2022 | Manuscript Accepted on 15 September 2022 | Manuscript published on 30 September 2022 | PP: 5-10 | Volume-2 Issue-2, September 2022. | Retrieval Number: 100.1/ijvlsid.B1210092222 | DOI: 10.54105/ijvlsid.B1210.092222
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Abstract: Static Random-Access Memory (SRAM) occupies approximately 90% of total area on a chip due to high number of transistors used for a single SRAM cell. Therefore, SRAM cell becomes a power-hungry block on a chip and it becomes more prominent at lower technologies from both dynamic and static perspective. Static power consumption is due to leakage current associated with the transistors that are off and dynamic power consumption is due to charging and discharging of the circuit capacitance. As gate length or channel length decreases gate oxide thickness also scales down. Scaling down of conventional transistor results in huge tunneling of electron from gate into channel leading to higher leakage power consumption. So, transistor with metal gate, high-k dielectric and strained-Si is used which shows better result in terms of low-power consumption, better performance with acceptable delay. Among various topologies of SRAM cell 6T is considered as a suitable choice for low power applications.
Keywords: SRAM, Metal Gate/ High-k/ Strained-Si, Metal Gate/ High-k, Power Consumption
Scope of the Article: VLSI Circuits and Design