Volume-3 Issue-1, March 2023 – Indian Journal of VLSI Design (IJVLSID) https://www.ijvlsi.latticescipub.com Exploring Innovation | ISSN: 2582-8843 (Online) | A Periodical Journal | Reg. No.: C/1383209 | Published by Lattice Science Publication (LSP) Sat, 19 Aug 2023 03:39:55 +0000 en-US hourly 1 https://wordpress.org/?v=6.9.4 https://www.ijvlsi.latticescipub.com/wp-content/uploads/2021/02/cropped-IJVLSID-WFS-1-32x32.png Volume-3 Issue-1, March 2023 – Indian Journal of VLSI Design (IJVLSID) https://www.ijvlsi.latticescipub.com 32 32 A1217033123 https://www.ijvlsi.latticescipub.com/portfolio-item/a1217033123/ Sat, 04 Mar 2023 13:23:51 +0000 https://www.ijvlsi.latticescipub.com/?post_type=portfolio&p=877 The Indian Journal of VLSI Design (IJVLSID) has ISSN 2582-8843 (online), open-access, peer-reviewed, periodical half-yearly international journal, which is published by Lattice Science Publication (LSP) in March and September. The journal aims to publish high-quality peer–reviewed original articles in the area of VLSI Design that covers VLSI Circuits and Design, Biological Computing, Computer-Aided Design (CAD), Fault-Tolerance, Emerging Technologies, Low Power and Power Aware Design, Molecular Computing, Nano Electronics Computing, Post-CMOS VLSI, Reliability, Testing, VLSI Applications (Communications, Video, Security, Sensor Networks), Quantum Computing and Wireless Communications. #VLSI Circuits and Design #Biological Computing #Computer-Aided Design (CAD) #Fault-Tolerance #Emerging Technologies #Low Power and Power Aware Design #Molecular Computing #Nano Electronics Computing #Post-CMOS VLSI #Reliability #Testing #VLSI Applications (Communications, Video, Security, Sensor Networks) #Quantum Computing #PhD ademic #Scopus #SCI #LatticeScience #Springer, #ScienceDirect #IEEE #Mendeley #Research #Scholarship #UGC #SSRN #LatticeScience #ESCI #Science #Journal #Conference #SSRN #PubLons

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]]> The Indian Journal of VLSI Design (IJVLSID) has ISSN 2582-8843 (online), open-access, peer-reviewed, periodical half-yearly international journal, which is published by Lattice Science Publication (LSP) in March and September. The journal aims to publish high-quality peer–reviewed original articles in the area of VLSI Design that covers VLSI Circuits and Design, Biological Computing, Computer-Aided Design (CAD), Fault-Tolerance, Emerging Technologies, Low Power and Power Aware Design, Molecular Computing, Nano Electronics Computing, Post-CMOS VLSI, Reliability, Testing, VLSI Applications (Communications, Video, Security, Sensor Networks), Quantum Computing and Wireless Communications. #VLSI Circuits and Design #Biological Computing #Computer-Aided Design (CAD) #Fault-Tolerance #Emerging Technologies #Low Power and Power Aware Design #Molecular Computing #Nano Electronics Computing #Post-CMOS VLSI #Reliability #Testing #VLSI Applications (Communications, Video, Security, Sensor Networks) #Quantum Computing #PhD ademic #Scopus #SCI #LatticeScience #Springer, #ScienceDirect #IEEE #Mendeley #Research #Scholarship #UGC #SSRN #LatticeScience #ESCI #Science #Journal #Conference #SSRN #PubLons

Review of 6T SRAM for Embedded Memory ApplicationsCROSSMARK Color horizontal
Pradeep Singh Yadav1, Harsha Jain2

1Pradeep Singh Yadav, Shri Shankaracharya Technical Campus, Bhilai (Chhattisgarh), India.

2Harsha Jain, Shri Shankaracharya Technical Campus, Bhilai (Chhattisgarh), India.

Manuscript received on 02 March 2023 | Revised Manuscript received on 04 March 2023 | Manuscript Accepted on 15 March 2023 | Manuscript published on 30 March 2023 | PP: 24-30 | Volume-3 Issue-1, March 2023 | Retrieval Number: 100.1/ijvlsid.A1217033123 | DOI: 10.54105/ijvlsid.A1217.033123

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© The Authors. Published by Lattice Science Publication (LSP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Due to the substantial impact embedded Static Random Access Memory (SRAM)s have on the overall system and their relatively limited design, it is essential to manage embedded SRAM trade-offs strategically. SRAMs have power, performance and density trade-offs in general. In all applications, all three dimensions are necessary to some extent; accordingly, embedded SRAM design must incorporate the most crucial system-specific requirements when developing embedded SRAM. This paper discusses many SRAM factors, including Static Noise Margin (SNM), Read Access Time (RAT),Write Access Time (WAT), Read Stability and Write Ability, Power, Data Retention Voltage (DRV), and Process Control. All these factors are crucial when designing SRAM for embedded memory applications. There has also been a discussion of the parameter comparisons and the literature review of the current papers.

Keywords: Area, Memory Application, Latency, Power, SNM, SRAM
Scope of the Article: VLSI Circuits and Design

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]]> A1215033123 https://www.ijvlsi.latticescipub.com/portfolio-item/a1215033123/ Sat, 25 Feb 2023 10:10:47 +0000 https://www.ijvlsi.latticescipub.com/?post_type=portfolio&p=864 The Indian Journal of VLSI Design (IJVLSID) has ISSN 2582-8843 (online), open-access, peer-reviewed, periodical half-yearly international journal, which is published by Lattice Science Publication (LSP) in March and September. The journal aims to publish high-quality peer–reviewed original articles in the area of VLSI Design that covers VLSI Circuits and Design, Biological Computing, Computer-Aided Design (CAD), Fault-Tolerance, Emerging Technologies, Low Power and Power Aware Design, Molecular Computing, Nano Electronics Computing, Post-CMOS VLSI, Reliability, Testing, VLSI Applications (Communications, Video, Security, Sensor Networks), Quantum Computing and Wireless Communications. #VLSI Circuits and Design #Biological Computing #Computer-Aided Design (CAD) #Fault-Tolerance #Emerging Technologies #Low Power and Power Aware Design #Molecular Computing #Nano Electronics Computing #Post-CMOS VLSI #Reliability #Testing #VLSI Applications (Communications, Video, Security, Sensor Networks) #Quantum Computing #PhD ademic #Scopus #SCI #LatticeScience #Springer, #ScienceDirect #IEEE #Mendeley #Research #Scholarship #UGC #SSRN #LatticeScience #ESCI #Science #Journal #Conference #SSRN #PubLons

The post A1215033123 appeared first on Indian Journal of VLSI Design (IJVLSID).

]]> The Indian Journal of VLSI Design (IJVLSID) has ISSN 2582-8843 (online), open-access, peer-reviewed, periodical half-yearly international journal, which is published by Lattice Science Publication (LSP) in March and September. The journal aims to publish high-quality peer–reviewed original articles in the area of VLSI Design that covers VLSI Circuits and Design, Biological Computing, Computer-Aided Design (CAD), Fault-Tolerance, Emerging Technologies, Low Power and Power Aware Design, Molecular Computing, Nano Electronics Computing, Post-CMOS VLSI, Reliability, Testing, VLSI Applications (Communications, Video, Security, Sensor Networks), Quantum Computing and Wireless Communications. #VLSI Circuits and Design #Biological Computing #Computer-Aided Design (CAD) #Fault-Tolerance #Emerging Technologies #Low Power and Power Aware Design #Molecular Computing #Nano Electronics Computing #Post-CMOS VLSI #Reliability #Testing #VLSI Applications (Communications, Video, Security, Sensor Networks) #Quantum Computing #PhD ademic #Scopus #SCI #LatticeScience #Springer, #ScienceDirect #IEEE #Mendeley #Research #Scholarship #UGC #SSRN #LatticeScience #ESCI #Science #Journal #Conference #SSRN #PubLons

A Comparative Study of CMOS Transimpedance Amplifier (TIA)CROSSMARK Color horizontal
Priya Singh1, Vandana Niranjan2, Ashwni Kumar3

1Priya Singh, Research Scholar, Indira Gandhi Delhi Technical University for Women, Kashmeri Gate, Delhi, India.

2Dr. Vandana Niranjan, Professor, Indira Gandhi Delhi Technical University for Women, Kashmeri Gate, Delhi, India.

3Prof. Ashwni Kumar, Professor, Indira Gandhi Delhi Technical University for Women, Kashmeri Gate, Delhi, India.

Manuscript received on 12 January 2023 | Revised Manuscript received on 25 February 2023 | Manuscript Accepted on 15 March 2023 | Manuscript published on 30 March 2023 | PP: 19-23 | Volume-3 Issue-1, March 2023. | Retrieval Number: 100.1/ijvlsid.A1215033123 | DOI: 10.54105/ijvlsid.A1215.033123

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© The Authors. Published by Lattice Science Publication (LSP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: In this paper a comparative study of different CMOS transimpedance amplifier has been presented. Standard device parameters of transimpedance amplifier such as gain, input refereed noise, power dissipation and group delay are studied and compared. Here the transimpedance amplifier is divided on the basis of its topology and device technology used and performance is summarized to get the overview. Most of the analysis taken are performed on 0.18 µm technology and some are implemented using 45nm, 0.13µm , 65nm , and 90nm.

Keywords: CMOS, Transimpedance, Amplifier (TIA), Technology
Scope of the Article: VLSI Circuits and Design

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]]> A1213033123 https://www.ijvlsi.latticescipub.com/portfolio-item/a1213033123/ Sat, 25 Feb 2023 10:01:40 +0000 https://www.ijvlsi.latticescipub.com/?post_type=portfolio&p=859 The Indian Journal of VLSI Design (IJVLSID) has ISSN 2582-8843 (online), open-access, peer-reviewed, periodical half-yearly international journal, which is published by Lattice Science Publication (LSP) in March and September. The journal aims to publish high-quality peer–reviewed original articles in the area of VLSI Design that covers VLSI Circuits and Design, Biological Computing, Computer-Aided Design (CAD), Fault-Tolerance, Emerging Technologies, Low Power and Power Aware Design, Molecular Computing, Nano Electronics Computing, Post-CMOS VLSI, Reliability, Testing, VLSI Applications (Communications, Video, Security, Sensor Networks), Quantum Computing and Wireless Communications. #VLSI Circuits and Design #Biological Computing #Computer-Aided Design (CAD) #Fault-Tolerance #Emerging Technologies #Low Power and Power Aware Design #Molecular Computing #Nano Electronics Computing #Post-CMOS VLSI #Reliability #Testing #VLSI Applications (Communications, Video, Security, Sensor Networks) #Quantum Computing #PhD ademic #Scopus #SCI #LatticeScience #Springer, #ScienceDirect #IEEE #Mendeley #Research #Scholarship #UGC #SSRN #LatticeScience #ESCI #Science #Journal #Conference #SSRN #PubLons

The post A1213033123 appeared first on Indian Journal of VLSI Design (IJVLSID).

]]> The Indian Journal of VLSI Design (IJVLSID) has ISSN 2582-8843 (online), open-access, peer-reviewed, periodical half-yearly international journal, which is published by Lattice Science Publication (LSP) in March and September. The journal aims to publish high-quality peer–reviewed original articles in the area of VLSI Design that covers VLSI Circuits and Design, Biological Computing, Computer-Aided Design (CAD), Fault-Tolerance, Emerging Technologies, Low Power and Power Aware Design, Molecular Computing, Nano Electronics Computing, Post-CMOS VLSI, Reliability, Testing, VLSI Applications (Communications, Video, Security, Sensor Networks), Quantum Computing and Wireless Communications. #VLSI Circuits and Design #Biological Computing #Computer-Aided Design (CAD) #Fault-Tolerance #Emerging Technologies #Low Power and Power Aware Design #Molecular Computing #Nano Electronics Computing #Post-CMOS VLSI #Reliability #Testing #VLSI Applications (Communications, Video, Security, Sensor Networks) #Quantum Computing #PhD ademic #Scopus #SCI #LatticeScience #Springer, #ScienceDirect #IEEE #Mendeley #Research #Scholarship #UGC #SSRN #LatticeScience #ESCI #Science #Journal #Conference #SSRN #PubLons

An Approach for the Reduction of Unwanted Edges in Contour Detection Based on Local FilteringCROSSMARK Color horizontal
Hadi Kolivand1, Azita Souri2

1Hadi Kolivand, Department of Electrical Engineering, Faculty of Engineering, Razi University, Tagh-E-Bostan, kermanshah, Iran.

2Azita Souri, Department of English language Education, Azad Islamic University, Touserkan, Iran.

Manuscript received on 10 November 2022 | Revised Manuscript received on 02 December 2022 | Manuscript Accepted on 15 March 2023 | Manuscript published on 30 March 2023 | PP: 11-18 | Volume-3 Issue-1, March 2023. | Retrieval Number: 100.1/ijvlsid.A1213033123 | DOI: 10.54105/ijvlsid.A1213.033123

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© The Authors. Published by Lattice Science Publication (LSP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: In this paper, an approach for the reduction of unwanted edges in contour detection based on local filtering is presented. Our approach can be used as a preprocessing step before contour detection. Also our approach is useful for object recognition based on feature extraction tasks, because many contour detection methods can’t delete all unwanted edges carefully. Our method consists of a computational algorithm that has 7 steps. Including smoothing, edge detection, smoothing, decreasing of pixels, thresholding, local filtering, and mask creation respectively. We use smoothing for adhering neighbor edge pixels and weakening alone edge pixels. So we can amplify the correct edge pixels and attenuate unwanted edge pixels by smoothing the edge image. In local filtering, we use a proposed casual template that determines noisy regions and correct regions and therefore can create a mask matrix that its elements related to mentioned regions. Finally we can use the “mask matrix” for improving contours by using a “And” operator and we ensure final contour that has a few context effect.

Keywords: Contour Detection, Edge Detection, Unwanted Edge, Local Filtering
Scope of the Article: VLSI Circuits and Design

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]]> A1216033123 https://www.ijvlsi.latticescipub.com/portfolio-item/a1216033123/ Sat, 28 Jan 2023 10:26:50 +0000 https://www.ijvlsi.latticescipub.com/?post_type=portfolio&p=824 The Indian Journal of VLSI Design (IJVLSID) has ISSN 2582-8843 (online), open-access, peer-reviewed, periodical half-yearly international journal, which is published by Lattice Science Publication (LSP) in March and September. The journal aims to publish high-quality peer–reviewed original articles in the area of VLSI Design that covers VLSI Circuits and Design, Biological Computing, Computer-Aided Design (CAD), Fault-Tolerance, Emerging Technologies, Low Power and Power Aware Design, Molecular Computing, Nano Electronics Computing, Post-CMOS VLSI, Reliability, Testing, VLSI Applications (Communications, Video, Security, Sensor Networks), Quantum Computing and Wireless Communications. #VLSI Circuits and Design #Biological Computing #Computer-Aided Design (CAD) #Fault-Tolerance #Emerging Technologies #Low Power and Power Aware Design #Molecular Computing #Nano Electronics Computing #Post-CMOS VLSI #Reliability #Testing #VLSI Applications (Communications, Video, Security, Sensor Networks) #Quantum Computing #PhD ademic #Scopus #SCI #LatticeScience #Springer, #ScienceDirect #IEEE #Mendeley #Research #Scholarship #UGC #SSRN #LatticeScience #ESCI #Science #Journal #Conference #SSRN #PubLons

The post A1216033123 appeared first on Indian Journal of VLSI Design (IJVLSID).

]]> The Indian Journal of VLSI Design (IJVLSID) has ISSN 2582-8843 (online), open-access, peer-reviewed, periodical half-yearly international journal, which is published by Lattice Science Publication (LSP) in March and September. The journal aims to publish high-quality peer–reviewed original articles in the area of VLSI Design that covers VLSI Circuits and Design, Biological Computing, Computer-Aided Design (CAD), Fault-Tolerance, Emerging Technologies, Low Power and Power Aware Design, Molecular Computing, Nano Electronics Computing, Post-CMOS VLSI, Reliability, Testing, VLSI Applications (Communications, Video, Security, Sensor Networks), Quantum Computing and Wireless Communications. #VLSI Circuits and Design #Biological Computing #Computer-Aided Design (CAD) #Fault-Tolerance #Emerging Technologies #Low Power and Power Aware Design #Molecular Computing #Nano Electronics Computing #Post-CMOS VLSI #Reliability #Testing #VLSI Applications (Communications, Video, Security, Sensor Networks) #Quantum Computing #PhD ademic #Scopus #SCI #LatticeScience #Springer, #ScienceDirect #IEEE #Mendeley #Research #Scholarship #UGC #SSRN #LatticeScience #ESCI #Science #Journal #Conference #SSRN #PubLons

Low Power Embedded SoC DesignCROSSMARK Color horizontal
G. Sasikala1, G. Satya Krishna2

1Dr. G. Sasikala, Department of Electronics and Communication Engineering, Vel Tech Rangarajan Dr. Sagunthala R&D Institute of Science and Technology, Morai (Tamil Nadu), India.

2G. Satya Krishna, Department of Electronics and Communication Engineering, Vel Tech Rangarajan Dr. Sagunthala R&D Institute of Science and Technology, Morai (Tamil Nadu), India.

Manuscript received on 14 January 2023 | Revised Manuscript received on 27 January 2023 | Manuscript Accepted on 15 March 2023 | Manuscript published on 30 March 2023 | PP: 1-10 | Volume-3 Issue-1, March 2023. | Retrieval Number: 100.1/ijvlsid.A1216033123 | DOI: 10.54105/ijvlsid.A1216.033123

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© The Authors. Published by Lattice Science Publication (LSP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Now a days all embedded processors are manufactured in such a way that it may consume low power to provide longer life to the system using various low power techniques like clock gating, data gating, variable frequency mechanism, variable voltage mechanism and variable threshold techniques. In this paper these techniques are implemented using VHDL language in Vivado and results are compared to identify the better one among all possible ones. There are various characteristics compared here are power consumption, number of look up tables and number of flip flops consumed.

Keywords: VHDL, Clock Gating, Data Gating, Frequency Scaling.
Scope of the Article: VLSI Circuits and Design

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