Three-Transistor Antifuse OTP Memory: Design, Simulation and Behavioral Verification
Jyoti Thakur1, Bhavesh Soni2
1Jyoti Thakur, Department of Electronics and Communication, Ganpat University, U. V. P. College of Engineering, Ganpat Vidyanagar, Gandhinagar (Gujarat), India.
2Prof. Bhavesh Soni, Assistant Professor, Department of Electronics and Communication, Ganpat University, U. V. P. College of Engineering, Ganpat Vidyanagar, Gandhinagar (Gujarat), India.
Manuscript received on 11 February 2026 | Revised Manuscript received on 13 March 2026 | Manuscript Accepted on 15 March 2026 | Manuscript published on 30 March 2026 | PP: 11-16 | Volume-6 Issue-1, March 2026 | Retrieval Number: 100.1/ijvlsid.B123506020926 | DOI: 10.54105/ijvlsid.B1235.06010326
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© The Authors. Published by Lattice Science Publication (LSP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper presents the plan for modelling and behavioural verification of a three-transistor antifuse-based OneTime Programmable (OTP) memory cell. This was execute using Verilog HDL and simulated within the Xilinx ISE 14.7 environment. This is a combination of an NMOS antifuse, a highvoltage blocking transistor, and an access transistor, which together enable permanent data storage through gate-oxide breakdown. A behavioural Verilog model is generated during the programming stage to change the antifuse resistance permanently. Its functionality was proved using ISim simulations. The simulations demonstrate reliable one-time programmability, stable data retention, or clear differentiation between programmed and unprogrammed states. Programming is achieved by activating the prog_en and vg_bt signals to lock the otp_bit node, followed by consistent read operations using the word line (wl) and bit line (bl). This memory cell is well-suited for System-on-Chip (SoC) integration, particularly for applications requiring secure cryptographic keys, unique device identifiers, calibration parameters, and configuration storage. The use of standard Verilog promotes rapid FPGA prototyping and seamless system deployment.
Keywords: 3T OTP Memory Cell, Antifuse-Based Memory, Verilog HDL Modelling, Gate Oxide Breakdown, Non-Volatile Storage, Xilinx ISE Simulation, One-Time Programmable, HighVoltage Blocking Transistor, Read Disturb Mitigation, SoC Integration.
Scope of the Article: Semiconductor