Implementation-Aware UPF Methodology for Managing Power Domain Crossings in Multi-Voltage SoCs
Aayush Gade1, Bhavesh Soni2, Dipesh Panchal3
1Aayush Gade, Department of Electronics & Communication Engineering, Ganpat University, Ahmedabad (Gujarat), India.
2Prof. Bhavesh Soni, Assistant Professor, Department of Electronics & Communication Engineering, Ganpat University, Ahmedabad (Gujarat), India.
3Dr. Dipesh Panchal, Senior Physical Design Engineer, Einfochips, an Arrow Company, Ahmedabad (Gujarat), India.
Manuscript received on 27 January 2026 | First Revised Manuscript received on 02 March 2026 | Second Revised Manuscript received on 10 March 2026 | Manuscript Accepted on 15 March 2026 | Manuscript published on 30 March 2026 | PP: 1-10 | Volume-6 Issue-1, March 2026 | Retrieval Number: 100.1/ijvlsid.A123306010326 | DOI: 10.54105/ijvlsid.A1233.06010326
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© The Authors. Published by Lattice Science Publication (LSP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Aggressive power targets in mobile, IoT, and automotive SoCs have driven extensive use of multi-voltage and power-gated domains, making power domain crossings a major source of overhead and bugs. Power in- tent is usually specified in UPF at a high level, and generic rules for isolation, level shifting, and retention are pushed into implementation, which can lead to an excessive number of special cells, timing loss, routing congestion, and difficult lowpower sign-off. This work proposes an implementation-aware power domain crossing (PDC) methodology tightly integrated with a Cadence Innovus-based flow. First, a clustering-based partitioning strategy groups strongly communicating blocks into common domains to minimise crossings and the number of special cells. Second, an optimised UPF boundary strategy tailors’ isolation, level-shifting, and retention policies to specific domain relationships and power modes, avoiding redundant instrumentation while preserving correctness. Third, a complete RTL → UPF → physical design flow is presented, with quantitative evaluation of area overhead, timing impact, power savings, and low-power verification violations against a conventional UPF baseline. Results for representative multidomain SoC subsystems show that the proposed approach significantly reduces domain crossings and special cells while maintaining sign-off quality, turning PDC from a late-implementation side effect into a controllable design parameter.
Keywords: Low-Power VLSI Design, Multi-Voltage SoC, Power Domain Crossings, Unified Power Format (UPF), Power Intent specification, Isolation and level Shifters, Retention Registers and Power Gating, Physical Design and Implementation (Cadence Innovus).
Scope of the Article: Microcontroller