B123606020926

Architectural Integration of Specialized Low-Power Cells and UPF Constraints in Nanoscale VLSI Design
Jesani Rutvik¹, Harsh Chauhan², Jenis Vekariya³, Dipesh Panchal⁴, Bhavesh Soni⁵

¹Rutvik Jesani, Department of Electronics and Communication, U. V. P. College of Engineering/Ganpat University, Ahmedabad (Gujarat), India.

²Harsh Chuhan, Studies, Department of Electronics and Communication, U. V. P. College of Engineering/Ganpat University, Ahmedabad (Gujarat), India.

³Jenis Vekariya, Studies, Department of Electronics and Communication, U. V. P. College of Engineering/Ganpat University, Ahmedabad (Gujarat), India.

⁴Dr. Dipesh Panchal, Department of Senior Physical Design Engineer, eInfochips/an Arrow Company, Ahmedabad (Gujarat), India.

⁵Prof. Bhavesh Soni, Faculty, U. V. P. College of Engineering, Ganpat University, Ahmedabad (Gujarat), India.       

Manuscript received on 25 March 2026 | First Revised Manuscript received on 31 March 2026 | Second Revised Manuscript received on 16 August 2026 | Manuscript Accepted on 15 September 2026 | Manuscript published on 30 September 2026 | PP: 1-7 | Volume-6 Issue-2, September 2026 | Retrieval Number: 100.1/ijvlsid.B123606020926 | DOI: 10.54105/ijvlsid.B1236.06020926

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© The Authors. Published by Lattice Science Publication (LSP). This is an open-access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: As integrated circuit fabrication advances deep into sub-10nm Fin FET dimensions, the primary challenge in physical design has decisively transitioned from minimizing silicon area to managing complex power demands. Modern multi-core SoCs require high-speed switching for computational performance, but this creates severe leakage and dynamic power dissipation issues. Consequently, developing a resilient, automated power intent architecture is essential. This work investigates the practical integration of advanced low-power VLSI components using the IEEE 1801 Unified Power Format (UPF). Specifically, we dissect the technical implementation of isolation cells, level shifters, and state-retention power-gating (SRPG) logic. A major focal point of our analysis is how UPF placement strategies differ— comparing” self-contained” intra-domain logic with” external” or “parent-level” cell insertion. We assess how these choices directly impact the physical design flow, particularly regarding floorplan constraints and power-grid congestion, ultimately showing their effects on final Power-Performance-Area (PPA) metrics. Finally, the study examines the specific Tcl syntax necessary to execute these strategies. This provides physical designers with a practical framework for selecting cell locations that reduce area overhead while ensuring functional reliability across various power states.

Keywords: CMOS VLSI Design, Low Power Methodology, Unified Power Format (UPF), IEEE 1801, Power Gating, MultiVoltage Architectures, Isolation Strategy, Level Shifters, State Retention Power Gating (SRPG), Physical Design Automation, Electronic Design Automation (EDA), Tcl Scripting, SubThreshold Leakage, Multi-Corner Multi-Mode (MCMM) Analysis.
Scope of the Article: Integrated Circuits (IC)