This paper presents the plan for modelling and behavioural verification of a three-transistor antifuse-based OneTime Programmable (OTP) memory cell. This was execute using Verilog HDL and simulated within the Xilinx ISE 14.7 environment. This is a combination of an NMOS antifuse, a highvoltage blocking transistor, and an access transistor, which together enable permanent data storage through gate-oxide breakdown. A behavioural Verilog model is generated during the programming stage to change the antifuse resistance permanently. Its functionality was proved using ISim simulations. The simulations demonstrate reliable one-time programmability, stable data retention, or clear differentiation between programmed and unprogrammed states. Programming is achieved by activating the prog_en and vg_bt signals to lock the otp_bit node, followed by consistent read operations using the word line (wl) and bit line (bl). This memory cell is well-suited for System-on-Chip (SoC) integration, particularly for applications requiring secure cryptographic keys, unique device identifiers, calibration parameters, and configuration storage. The use of standard Verilog promotes rapid FPGA prototyping and seamless system deployment.

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Aggressive power targets in mobile, IoT, and automotive SoCs have driven extensive use of multi-voltage and power-gated domains, making power domain crossings a major source of overhead and bugs. Power in- tent is usually specified in UPF at a high level, and generic rules for isolation, level shifting, and retention are pushed into implementation, which can lead to an excessive number of special cells, timing loss, routing congestion, and difficult lowpower sign-off. This work proposes an implementation-aware power domain crossing (PDC) methodology tightly integrated with a Cadence Innovus-based flow. First, a clustering-based partitioning strategy groups strongly communicating blocks into common domains to minimise crossings and the number of special cells. Second, an optimised UPF boundary strategy tailors’ isolation, level-shifting, and retention policies to specific domain relationships and power modes, avoiding redundant instrumentation while preserving correctness. Third, a complete RTL → UPF → physical design flow is presented, with quantitative evaluation of area overhead, timing impact, power savings, and low-power verification violations against a conventional UPF baseline. Results for representative multidomain SoC subsystems show that the proposed approach significantly reduces domain crossings and special cells while maintaining sign-off quality, turning PDC from a late-implementation side effect into a controllable design parameter.

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