Volume-2 Issue-1, March 2022 – Indian Journal of VLSI Design (IJVLSID) https://www.ijvlsi.latticescipub.com Exploring Innovation | ISSN: 2582-8843 (Online) | A Periodical Journal | Reg. No.: C/1383209 | Published by Lattice Science Publication (LSP) Sat, 19 Aug 2023 03:50:19 +0000 en-US hourly 1 https://wordpress.org/?v=7.0 https://www.ijvlsi.latticescipub.com/wp-content/uploads/2021/02/cropped-IJVLSID-WFS-1-32x32.png Volume-2 Issue-1, March 2022 – Indian Journal of VLSI Design (IJVLSID) https://www.ijvlsi.latticescipub.com 32 32 C1207031322 https://www.ijvlsi.latticescipub.com/portfolio-item/c1207031322/ https://www.ijvlsi.latticescipub.com/portfolio-item/c1207031322/#respond Fri, 11 Mar 2022 12:08:02 +0000 https://www.ijvlsi.latticescipub.com/?post_type=portfolio&p=584 The Indian Journal of VLSI Design (IJVLSID) has ISSN 2582-8843 (online), open-access, peer-reviewed, periodical half-yearly international journal, which is published by Lattice Science Publication (LSP) in March and September. The journal aims to publish high-quality peer–reviewed original articles in the area of VLSI Design that covers VLSI Circuits and Design, Biological Computing, Computer-Aided Design (CAD), Fault-Tolerance, Emerging Technologies, Low Power and Power Aware Design, Molecular Computing, Nano Electronics Computing, Post-CMOS VLSI, Reliability, Testing, VLSI Applications (Communications, Video, Security, Sensor Networks), Quantum Computing and Wireless Communications. #VLSI Circuits and Design #Biological Computing #Computer-Aided Design (CAD) #Fault-Tolerance #Emerging Technologies #Low Power and Power Aware Design #Molecular Computing #Nano Electronics Computing #Post-CMOS VLSI #Reliability #Testing #VLSI Applications (Communications, Video, Security, Sensor Networks) #Quantum Computing #PhD ademic #Scopus #SCI #LatticeScience #Springer, #ScienceDirect #IEEE #Mendeley #Research #Scholarship #UGC #SSRN #LatticeScience #ESCI #Science #Journal #Conference #SSRN #PubLons

The post C1207031322 appeared first on Indian Journal of VLSI Design (IJVLSID).

]]> The Indian Journal of VLSI Design (IJVLSID) has ISSN 2582-8843 (online), open-access, peer-reviewed, periodical half-yearly international journal, which is published by Lattice Science Publication (LSP) in March and September. The journal aims to publish high-quality peer–reviewed original articles in the area of VLSI Design that covers VLSI Circuits and Design, Biological Computing, Computer-Aided Design (CAD), Fault-Tolerance, Emerging Technologies, Low Power and Power Aware Design, Molecular Computing, Nano Electronics Computing, Post-CMOS VLSI, Reliability, Testing, VLSI Applications (Communications, Video, Security, Sensor Networks), Quantum Computing and Wireless Communications. #VLSI Circuits and Design #Biological Computing #Computer-Aided Design (CAD) #Fault-Tolerance #Emerging Technologies #Low Power and Power Aware Design #Molecular Computing #Nano Electronics Computing #Post-CMOS VLSI #Reliability #Testing #VLSI Applications (Communications, Video, Security, Sensor Networks) #Quantum Computing #PhD ademic #Scopus #SCI #LatticeScience #Springer, #ScienceDirect #IEEE #Mendeley #Research #Scholarship #UGC #SSRN #LatticeScience #ESCI #Science #Journal #Conference #SSRN #PubLons

Analysis of Velocity Measurement of Radar Signal in Space Vehicle Application using VLSI ChipCROSSMARK Color horizontal
E. N. Ganesh

Dr. E. N. Ganesh, Department of Electronics & Communication Engineering, Vels University, Chennai, (Tamil Nadu), India.

Manuscript received on 03 February 2022 | Revised Manuscript received on 11 March 2022 | Manuscript Accepted on 15 March 2022 | Manuscript published on 30 March 2022 | PP: 16-20 | Volume-2 Issue-1, March 2022. | Retrieval Number: 100.1/ijvlsid.C1207031322 | DOI: 10.54105/ijvlsid.C1207.031322

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© The Authors. Published by Lattice Science Publication (LSP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: The objective of the project is to design a low cost Spectral Monitor for a Space vehicle velocity measurement application, based on Doppler Shift principle by generating an radar signal source from earth station towards moving target device in space and processing received high speed analog 200MHz radar signal from target vehicle device through Antenna, analog pre-processing and FPGA based spectral analyzer. The hardware reconfigurable spectral analyzer design consist of ADC(500MSPS) Interface block, SRAM Memory(1024×16) block, Radix-2 FFT (16 bit DSP block) and LCD Display (Monitoring) driver algorithm implemented On-Chip SOC-FPGA system. The proposed algorithm can be used to meet the need of many real time application such as space exploration, wideband communication, command and control application. The desired algorithm is implemented on-chip reconfigurable hardware SOC-FPGA while keeping the cost, power and area of device low compared to general purpose processor and Embedded based microcontroller. The code architecture is described using hardware description language, VHDL and synthesized and simulated using Xilinx 12.2 ISE Design suite.

Keywords: System on Chip (SOC), Field Programmable Gate Array (FPGA), Analog to Digital Conversion (ADC), Hardware Descriptive Language (HDL), Fast Fourier Transform (FFT).
Scope of the Article: VLSI Circuits and Design

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]]> https://www.ijvlsi.latticescipub.com/portfolio-item/c1207031322/feed/ 0 C1206031322 https://www.ijvlsi.latticescipub.com/portfolio-item/c1206031322/ https://www.ijvlsi.latticescipub.com/portfolio-item/c1206031322/#respond Thu, 10 Feb 2022 09:56:38 +0000 https://www.ijvlsi.latticescipub.com/?post_type=portfolio&p=571 The Indian Journal of VLSI Design (IJVLSID) has ISSN 2582-8843 (online), open-access, peer-reviewed, periodical half-yearly international journal, which is published by Lattice Science Publication (LSP) in March and September. The journal aims to publish high-quality peer–reviewed original articles in the area of VLSI Design that covers VLSI Circuits and Design, Biological Computing, Computer-Aided Design (CAD), Fault-Tolerance, Emerging Technologies, Low Power and Power Aware Design, Molecular Computing, Nano Electronics Computing, Post-CMOS VLSI, Reliability, Testing, VLSI Applications (Communications, Video, Security, Sensor Networks), Quantum Computing and Wireless Communications. #VLSI Circuits and Design #Biological Computing #Computer-Aided Design (CAD) #Fault-Tolerance #Emerging Technologies #Low Power and Power Aware Design #Molecular Computing #Nano Electronics Computing #Post-CMOS VLSI #Reliability #Testing #VLSI Applications (Communications, Video, Security, Sensor Networks) #Quantum Computing #PhD ademic #Scopus #SCI #LatticeScience #Springer, #ScienceDirect #IEEE #Mendeley #Research #Scholarship #UGC #SSRN #LatticeScience #ESCI #Science #Journal #Conference #SSRN #PubLons

The post C1206031322 appeared first on Indian Journal of VLSI Design (IJVLSID).

]]> The Indian Journal of VLSI Design (IJVLSID) has ISSN 2582-8843 (online), open-access, peer-reviewed, periodical half-yearly international journal, which is published by Lattice Science Publication (LSP) in March and September. The journal aims to publish high-quality peer–reviewed original articles in the area of VLSI Design that covers VLSI Circuits and Design, Biological Computing, Computer-Aided Design (CAD), Fault-Tolerance, Emerging Technologies, Low Power and Power Aware Design, Molecular Computing, Nano Electronics Computing, Post-CMOS VLSI, Reliability, Testing, VLSI Applications (Communications, Video, Security, Sensor Networks), Quantum Computing and Wireless Communications. #VLSI Circuits and Design #Biological Computing #Computer-Aided Design (CAD) #Fault-Tolerance #Emerging Technologies #Low Power and Power Aware Design #Molecular Computing #Nano Electronics Computing #Post-CMOS VLSI #Reliability #Testing #VLSI Applications (Communications, Video, Security, Sensor Networks) #Quantum Computing #PhD ademic #Scopus #SCI #LatticeScience #Springer, #ScienceDirect #IEEE #Mendeley #Research #Scholarship #UGC #SSRN #LatticeScience #ESCI #Science #Journal #Conference #SSRN #PubLons

A Comparative Analysis of Gain and Bandwidth of CMOS Transimpedance Amplifier CROSSMARK Color horizontal
Vineeta Singh1, Sarika Parihar2, Vandana Niranjan3

1Vineeta Singh, Department of Electronics and Communication Engineering, Indira Gandhi Delhi Technical University, for Women New Delhi, India.

2Sarika Parihar, Department of Electronics and Communication Engineering, Indira Gandhi Delhi Technical University, for Women New Delhi, India.

3Vandana Niranjan, Department of Electronics and Communication Engineering, Indira Gandhi Delhi Technical University, for Women New Delhi, India.

Manuscript received on 24 January 2022 | Revised Manuscript received on 06 February 2022 | Manuscript Accepted on 15 March 2022 | Manuscript published on 30 March 2022 | PP: 10-15 | Volume-2 Issue-1, March 2022. | Retrieval Number: 100.1/ijvlsid.C1206031322 | DOI: 10.54105/ijvlsid.C1206.031322

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© The Authors. Published by Lattice Science Publication (LSP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: The paper presents the various trans-impedance amplifier (TIA) topologies has been studied and presented with an insight of their Gain and Bandwidth. The device parameters such as gain and bandwidth has been studied and compared for various TIA topologies. The performance of the presented topologies of TIA has been compared and summarized to get an overview. The comparison is done on the basis of its topology and device technology along with gain, bandwidth and power supply. In this paper recent advancement and future scope are also discussed.

Keywords: Trans-Impedance Amplifier (Tia), Topology, High Gain, Bandwidth.
Scope of the Article: VLSI Circuits and Design

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]]> https://www.ijvlsi.latticescipub.com/portfolio-item/c1206031322/feed/ 0 C1205031322 https://www.ijvlsi.latticescipub.com/portfolio-item/c1205031322/ https://www.ijvlsi.latticescipub.com/portfolio-item/c1205031322/#respond Sat, 18 Dec 2021 10:04:39 +0000 https://www.ijvlsi.latticescipub.com/?post_type=portfolio&p=526 The Indian Journal of VLSI Design (IJVLSID) has ISSN 2582-8843 (online), open-access, peer-reviewed, periodical half-yearly international journal, which is published by Lattice Science Publication (LSP) in March and September. The journal aims to publish high-quality peer–reviewed original articles in the area of VLSI Design that covers VLSI Circuits and Design, Biological Computing, Computer-Aided Design (CAD), Fault-Tolerance, Emerging Technologies, Low Power and Power Aware Design, Molecular Computing, Nano Electronics Computing, Post-CMOS VLSI, Reliability, Testing, VLSI Applications (Communications, Video, Security, Sensor Networks), Quantum Computing and Wireless Communications. #VLSI Circuits and Design #Biological Computing #Computer-Aided Design (CAD) #Fault-Tolerance #Emerging Technologies #Low Power and Power Aware Design #Molecular Computing #Nano Electronics Computing #Post-CMOS VLSI #Reliability #Testing #VLSI Applications (Communications, Video, Security, Sensor Networks) #Quantum Computing #PhD ademic #Scopus #SCI #LatticeScience #Springer, #ScienceDirect #IEEE #Mendeley #Research #Scholarship #UGC #SSRN #LatticeScience #ESCI #Science #Journal #Conference #SSRN #PubLons

The post C1205031322 appeared first on Indian Journal of VLSI Design (IJVLSID).

]]> The Indian Journal of VLSI Design (IJVLSID) has ISSN 2582-8843 (online), open-access, peer-reviewed, periodical half-yearly international journal, which is published by Lattice Science Publication (LSP) in March and September. The journal aims to publish high-quality peer–reviewed original articles in the area of VLSI Design that covers VLSI Circuits and Design, Biological Computing, Computer-Aided Design (CAD), Fault-Tolerance, Emerging Technologies, Low Power and Power Aware Design, Molecular Computing, Nano Electronics Computing, Post-CMOS VLSI, Reliability, Testing, VLSI Applications (Communications, Video, Security, Sensor Networks), Quantum Computing and Wireless Communications. #VLSI Circuits and Design #Biological Computing #Computer-Aided Design (CAD) #Fault-Tolerance #Emerging Technologies #Low Power and Power Aware Design #Molecular Computing #Nano Electronics Computing #Post-CMOS VLSI #Reliability #Testing #VLSI Applications (Communications, Video, Security, Sensor Networks) #Quantum Computing #PhD ademic #Scopus #SCI #LatticeScience #Springer, #ScienceDirect #IEEE #Mendeley #Research #Scholarship #UGC #SSRN #LatticeScience #ESCI #Science #Journal #Conference #SSRN #PubLons

Design of Carry Select Adder using BEC and Common Boolean Logic CROSSMARK Color horizontal
Syed Mustafaa M1, Sathish M2, Nivedha S3, Mohammed Magribatul Noora A K4, Safrin Sifana5

1Syed Mustafaa M, Department of Electronics and Communications Engineering, Aalim Muhammed Salegh College of Engineering, Chennai, India.

2Sathish M, Department of Electronics and Communications Engineering, Aalim Muhammed Salegh College of Engineering, Chennai, India.

3Nivedha S, Department of Electronics and Communications Engineering, Aalim Muhammed Salegh College of Engineering, Chennai, India.

4Magribatul Noora A K, Department of Electronics and Communications Engineering, Aalim Muhammed Salegh College of Engineering, Chennai, India.

5Safrin Sifana T, Department of Electronics and Communications Engineering, Aalim Muhammed Salegh College of Engineering, Chennai, India.

Manuscript received on 03 December 2021 | Revised Manuscript received on 14 December 2021 | Manuscript Accepted on 15 March 2022 | Manuscript published on 30 March 2022 | PP: 5-9 | Volume-2 Issue-1, March 2022. | Retrieval Number: 100.1/ijvlsid.C1205031322 | DOI: 10.54105/ijvlsid.C1205.031322

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© The Authors. Published by Lattice Science Publication (LSP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Carry Select Adder (CSLA) is known to be the fastest adder among the conventional adder structure, which uses multiple narrow adders. CSLA has a great scope of reducing area, power consumption, speed and delay. From the structure of regular CSLA using RCA, it consumes large area and power. This proposed work uses a simple and dynamic Gate Level Implementation which reduces the area, delay, power and speed of the regular CSLA. Based on a modified CSLA using BEC the implementation of 8-b, 16-b, 32-b square root CSLA (SQRT CSLA) architecture have been developed. In order to reduce the area and power consumption in a great way we proposed a design using binary to excess 1 converter (BEC). This paper proposes an dynamic method which replaces a BEC using Common Boolean Logic.

Keywords: SQRT CSLA, BEC, CBL.
Scope of the Article: VLSI Circuits and Design

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]]> https://www.ijvlsi.latticescipub.com/portfolio-item/c1205031322/feed/ 0 C1204031322 https://www.ijvlsi.latticescipub.com/portfolio-item/c1204031322/ https://www.ijvlsi.latticescipub.com/portfolio-item/c1204031322/#respond Mon, 01 Nov 2021 06:14:46 +0000 https://www.ijvlsi.latticescipub.com/?post_type=portfolio&p=497 The Indian Journal of VLSI Design (IJVLSID) has ISSN 2582-8843 (online), open-access, peer-reviewed, periodical half-yearly international journal, which is published by Lattice Science Publication (LSP) in March and September. The journal aims to publish high-quality peer–reviewed original articles in the area of VLSI Design that covers VLSI Circuits and Design, Biological Computing, Computer-Aided Design (CAD), Fault-Tolerance, Emerging Technologies, Low Power and Power Aware Design, Molecular Computing, Nano Electronics Computing, Post-CMOS VLSI, Reliability, Testing, VLSI Applications (Communications, Video, Security, Sensor Networks), Quantum Computing and Wireless Communications. #VLSI Circuits and Design #Biological Computing #Computer-Aided Design (CAD) #Fault-Tolerance #Emerging Technologies #Low Power and Power Aware Design #Molecular Computing #Nano Electronics Computing #Post-CMOS VLSI #Reliability #Testing #VLSI Applications (Communications, Video, Security, Sensor Networks) #Quantum Computing #PhD ademic #Scopus #SCI #LatticeScience #Springer, #ScienceDirect #IEEE #Mendeley #Research #Scholarship #UGC #SSRN #LatticeScience #ESCI #Science #Journal #Conference #SSRN #PubLons

The post C1204031322 appeared first on Indian Journal of VLSI Design (IJVLSID).

]]> The Indian Journal of VLSI Design (IJVLSID) has ISSN 2582-8843 (online), open-access, peer-reviewed, periodical half-yearly international journal, which is published by Lattice Science Publication (LSP) in March and September. The journal aims to publish high-quality peer–reviewed original articles in the area of VLSI Design that covers VLSI Circuits and Design, Biological Computing, Computer-Aided Design (CAD), Fault-Tolerance, Emerging Technologies, Low Power and Power Aware Design, Molecular Computing, Nano Electronics Computing, Post-CMOS VLSI, Reliability, Testing, VLSI Applications (Communications, Video, Security, Sensor Networks), Quantum Computing and Wireless Communications. #VLSI Circuits and Design #Biological Computing #Computer-Aided Design (CAD) #Fault-Tolerance #Emerging Technologies #Low Power and Power Aware Design #Molecular Computing #Nano Electronics Computing #Post-CMOS VLSI #Reliability #Testing #VLSI Applications (Communications, Video, Security, Sensor Networks) #Quantum Computing #PhD ademic #Scopus #SCI #LatticeScience #Springer, #ScienceDirect #IEEE #Mendeley #Research #Scholarship #UGC #SSRN #LatticeScience #ESCI #Science #Journal #Conference #SSRN #PubLons

Hybrid Renewable Energy Generation Through Incremental Conductance MpptCROSSMARK Color horizontal
Shurbhit Surage1, M.P.S. Chawla2

1Shurbhit Surage, Department of Electrical Engineering, SGSITS, Indore (M.P.), India.

2M.P.S. Chawla, Department of Electrical Engineering, SGSITS, Indore (M.P.), India.

Manuscript received on 19 October 2021 | Revised Manuscript received on 10 October 2021 | Manuscript Accepted on 15 March 2022 | Manuscript published on 30 March 2022 | PP: 1-4 | Volume-`2 Issue-1, March 2022. | Retrieval Number: 100.1/ijvlsid.C1204031322 | DOI: 10.54105/ijvlsid.C1204.031322

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© The Authors. Published by Lattice Science Publication (LSP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: The relevance of electricity generation from renewable energy sources is growing every day in the current global energy environment. The scarcity of fossil fuels and the environmental risks connected with traditional power producing methods are the main reasons behind this. The major sources of non-conventional energy are wind and solar which can be harnessed easily. A new system design for hybrid photovoltaic and wind-power generation is introduced within this study. A Modified M.P.P.T. has been proposed to strengthen productivity of this system. The proposed approach employs the Incremental Conductance (IC) MPPT technique. Under varied climatic conditions (Solar irradiance & Temperature), IC is utilized to determine the optimum voltage output of a photo voltaic generator (P.V.G.) within the photo voltaic system (P.V.) structure. The Incremental Conductance is utilized to manage the converter’s technology having boosting function. The P.M.S.G. is used to determine the maximum voltage output for varied wind flow rates in wind turbine system. Simulations are conducted in Matlab2019b to test efficacy of the proposed MPPT. The proposed scheme’s effectiveness can be supported with simulation results.

Keywords: Incremental Conductance, MPPT, Renewable Hybrid Energy, Solar PV, Wind PMSG.
Scope of the Article: Hybrid Renewable Energy

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